Openings Overview

Stage 1 — Spartan

SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{LeftInstructionInput}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{RightInstructionInput}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{Product}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{WriteLookupOutputToRD}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{WritePCtoRD}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{ShouldBranch}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{PC}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{UnexpandedPC}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{Imm}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{RamAddress}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{Rs1Value}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{Rs2Value}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{RdWriteValue}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{RamReadValue}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{RamWriteValue}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{LeftLookupOperand}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{RightLookupOperand}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{NextUnexpandedPC}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{NextPC}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{NextIsVirtual}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{NextIsFirstInSequence}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{LookupOutput}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{ShouldJump}}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{AddOperands})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{SubtractOperands})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{MultiplyOperands})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{Load})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{Store})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{Jump})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{WriteLookupOutputToRD})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{VirtualInstruction})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{Assert})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{DoNotUpdateUnexpandedPC})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{Advice})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{IsCompressed})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{IsFirstInSequence})}(r_{\text{cycle}}^{(1)})$
SpartanOuter (Stage 1) → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{IsLastInSequence})}(r_{\text{cycle}}^{(1)})$

Stage 2 — Virtualization & RAM

SpartanProductVirtualization → $\textcolor{BurntOrange}{\textsf{LeftInstructionInput}}(r_{\text{cycle}}^{(2)})$
SpartanProductVirtualization → $\textcolor{BurntOrange}{\textsf{RightInstructionInput}}(r_{\text{cycle}}^{(2)})$
SpartanProductVirtualization → $\textcolor{BurntOrange}{\textsf{InstructionFlags}(\text{IsRdNotZero})}(r_{\text{cycle}}^{(2)})$
SpartanProductVirtualization → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{WriteLookupOutputToRD})}(r_{\text{cycle}}^{(2)})$
SpartanProductVirtualization → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{Jump})}(r_{\text{cycle}}^{(2)})$
SpartanProductVirtualization → $\textcolor{BurntOrange}{\textsf{LookupOutput}}(r_{\text{cycle}}^{(2)})$
SpartanProductVirtualization → $\textcolor{BurntOrange}{\textsf{InstructionFlags}(\text{Branch})}(r_{\text{cycle}}^{(2)})$
SpartanProductVirtualization → $\textcolor{BurntOrange}{\textsf{NextIsNoop}}(r_{\text{cycle}}^{(2)})$
SpartanProductVirtualization → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{VirtualInstruction})}(r_{\text{cycle}}^{(2)})$
RamReadWriteChecking → $\textcolor{BurntOrange}{\textsf{RamVal}}(r_{K_{\text{ram}}}^{(2)}, r_{\text{cycle}}^{(2)})$
RamReadWriteChecking → $\textcolor{BurntOrange}{\textsf{RamRa}}(r_{K_{\text{ram}}}^{(2)}, r_{\text{cycle}}^{(2)})$
RamReadWriteChecking → $\textcolor{ForestGreen}{\textsf{RamInc}}(r_{\text{cycle}}^{(2)})$
InstructionClaimReduction → $\textcolor{BurntOrange}{\textsf{LookupOutput}}(r_{\text{cycle}}^{(2)})$
InstructionClaimReduction → $\textcolor{BurntOrange}{\textsf{LeftLookupOperand}}(r_{\text{cycle}}^{(2)})$
InstructionClaimReduction → $\textcolor{BurntOrange}{\textsf{RightLookupOperand}}(r_{\text{cycle}}^{(2)})$
InstructionClaimReduction → $\textcolor{BurntOrange}{\textsf{LeftInstructionInput}}(r_{\text{cycle}}^{(2)})$
InstructionClaimReduction → $\textcolor{BurntOrange}{\textsf{RightInstructionInput}}(r_{\text{cycle}}^{(2)})$
RamRafEvaluation → $\textcolor{BurntOrange}{\textsf{RamRa}}(r_{K_{\text{ram}}}^{(2)}, r_{\text{cycle}}^{(1)})$
RamOutputCheck → $\textcolor{BurntOrange}{\textsf{RamValFinal}}(r_{K_{\text{ram}}}^{(2)})$

Stage 3 — Shift & Instruction Input

Shift → $\textcolor{BurntOrange}{\textsf{UnexpandedPC}}(r_{\text{cycle}}^{(3)})$
Shift → $\textcolor{BurntOrange}{\textsf{PC}}(r_{\text{cycle}}^{(3)})$
Shift → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{VirtualInstruction})}(r_{\text{cycle}}^{(3)})$
Shift → $\textcolor{BurntOrange}{\textsf{OpFlags}(\text{IsFirstInSequence})}(r_{\text{cycle}}^{(3)})$
Shift → $\textcolor{BurntOrange}{\textsf{InstructionFlags}(\text{IsNoop})}(r_{\text{cycle}}^{(3)})$
InstructionInput → $\textcolor{BurntOrange}{\textsf{InstructionFlags}(\text{LeftOperandIsRs1Value})}(r_{\text{cycle}}^{(3)})$
InstructionInput → $\textcolor{BurntOrange}{\textsf{Rs1Value}}(r_{\text{cycle}}^{(3)})$
InstructionInput → $\textcolor{BurntOrange}{\textsf{InstructionFlags}(\text{LeftOperandIsPC})}(r_{\text{cycle}}^{(3)})$
InstructionInput → $\textcolor{BurntOrange}{\textsf{UnexpandedPC}}(r_{\text{cycle}}^{(3)})$
InstructionInput → $\textcolor{BurntOrange}{\textsf{InstructionFlags}(\text{RightOperandIsRs2Value})}(r_{\text{cycle}}^{(3)})$
InstructionInput → $\textcolor{BurntOrange}{\textsf{Rs2Value}}(r_{\text{cycle}}^{(3)})$
InstructionInput → $\textcolor{BurntOrange}{\textsf{InstructionFlags}(\text{RightOperandIsImm})}(r_{\text{cycle}}^{(3)})$
InstructionInput → $\textcolor{BurntOrange}{\textsf{Imm}}(r_{\text{cycle}}^{(3)})$
RegistersClaimReduction → $\textcolor{BurntOrange}{\textsf{RdWriteValue}}(r_{\text{cycle}}^{(3)})$
RegistersClaimReduction → $\textcolor{BurntOrange}{\textsf{Rs1Value}}(r_{\text{cycle}}^{(3)})$
RegistersClaimReduction → $\textcolor{BurntOrange}{\textsf{Rs2Value}}(r_{\text{cycle}}^{(3)})$

Stage 4 — Registers & RAM Val

RegistersReadWriteChecking → $\textcolor{BurntOrange}{\textsf{RegistersVal}}(r_{K_{\text{reg}}}^{(4)}, r_{\text{cycle}}^{(4)})$
RegistersReadWriteChecking → $\textcolor{BurntOrange}{\textsf{Rs1Ra}}(r_{K_{\text{reg}}}^{(4)}, r_{\text{cycle}}^{(4)})$
RegistersReadWriteChecking → $\textcolor{BurntOrange}{\textsf{Rs2Ra}}(r_{K_{\text{reg}}}^{(4)}, r_{\text{cycle}}^{(4)})$
RegistersReadWriteChecking → $\textcolor{BurntOrange}{\textsf{RdWa}}(r_{K_{\text{reg}}}^{(4)}, r_{\text{cycle}}^{(4)})$
RegistersReadWriteChecking → $\textcolor{ForestGreen}{\textsf{RdInc}}(r_{\text{cycle}}^{(4)})$
RamValCheck → $\textcolor{ForestGreen}{\textsf{RamInc}}(r_{\text{cycle}}^{(4)})$
RamValCheck → $\textcolor{BurntOrange}{\textsf{RamRa}}(r_{K_{\text{ram}}}^{(2)}, r_{\text{cycle}}^{(4)})$

Stage 5 — Instruction Read RAF & Reductions

InstructionReadRaf → $\textsf{InstructionRa}(i)(r_{K_{\text{instr}}^{(i)}}^{(5)}, r_{\text{cycle}}^{(5)}) \text{ for } i=0,\ldots,d_v-1$
InstructionReadRaf → $\textsf{TableFlag}(j)(r_{\text{cycle}}^{(5)}) \text{ for } j=0,\ldots,N_{\text{tables}}-1$
InstructionReadRaf → $\textcolor{BurntOrange}{\textsf{InstructionRafFlag}}(r_{\text{cycle}}^{(5)})$
RamRaClaimReduction → $\textcolor{BurntOrange}{\textsf{RamRa}}(r_{K_{\text{ram}}}^{(2)}, r_{\text{cycle}}^{(5)})$
RegistersValEvaluation → $\textcolor{ForestGreen}{\textsf{RdInc}}(r_{\text{cycle}}^{(5)})$
RegistersValEvaluation → $\textcolor{BurntOrange}{\textsf{RdWa}}(r_{K_{\text{reg}}}^{(4)}, r_{\text{cycle}}^{(5)})$

Stage 6 — Booleanity, Bytecode & Virtualization

RamHammingBooleanity → $\textcolor{BurntOrange}{\textsf{RamHammingWeight}}(r_{\text{cycle}}^{(6)})$
IncClaimReduction → $\textcolor{ForestGreen}{\textsf{RamInc}}(r_{\text{cycle}}^{(6)})$
IncClaimReduction → $\textcolor{ForestGreen}{\textsf{RdInc}}(r_{\text{cycle}}^{(6)})$
BytecodeReadRaf → $\textcolor{ForestGreen}{\textsf{BytecodeRa}(i)}(r_{K_{\text{bc}}^{(i)}}^{(6)}, r_{\text{cycle}}^{(6)}) \text{ for } i=0,\ldots,d_{\text{bc}}-1$
InstructionRaVirtualization → $\textsf{InstructionRa}(j)(r_{K^{(j)}}^{(5)}, r_{\text{cycle}}^{(6)}) \text{ for } j=0,\ldots,d_{\text{instr}}-1$
RamRaVirtualization → $\textcolor{ForestGreen}{\textsf{RamRa}(i)}(r_{K_{\text{ram}}^{(i)}}^{(2)}, r_{\text{cycle}}^{(6)}) \text{ for } i=0,\ldots,d_{\text{ram}}-1$
Booleanity → $\textsf{Ra}_{j}(r_{\text{addr}}^{(6)}, r_{\text{cycle}}^{(6)}) \text{ for } j=0,\ldots,d-1 (d = d_{\text{instr}} + d_{\text{bc}} + d_{\text{ram}})$

Stage 7 — Hamming Weight Claim Reduction

HammingWeightClaimReduction → $\textsf{Ra}_{j}(r_{\text{addr}}^{(7)}, r_{\text{cycle}}^{(6)}) \text{ for } j=0,\ldots,N_{\text{ra}}-1 (N_{\text{ra}} = d_{\text{instr}} + d_{\text{bc}} + d_{\text{ram}})$