Jolt-Qed

This series describes the efforts to formally verify using the Lean proof assistant that the Jolt bytecode expansions faithfully represent their corresponding RISC-V instructions.

  1. Automatic Bytecode Expansion Extraction
  2. Jolt System Mismatch
  3. How to Model a CPU in Lean
  4. Jolt: Introduction
  5. Equivalence Statements And Assumptions
  6. Bug Report: DIVW Inline Sequence Incompleteness